1. Field of the Invention
The present invention is related to the field of circuit design. In particular, the present invention is related to a method and apparatus to insert clocked and non-clocked repeaters in a circuit design.
2. Description of the Related Art
Interconnect optimization is a critical component of circuit design, and in particular, of Very Large Scale Integration (VLSI) circuit designs. As part of interconnect optimization of a VLSI circuit design, repeaters (e.g., buffers and inverters) are used to reduce interconnect delay and to meet transition time/noise constraints. However, merely using repeaters does not solve all timing requirements; for example, when wire delay is greater than a clock cycle, the addition of repeaters may not solve the timing constraints and the insertion of clocked repeaters (e.g. flip-flops and/or latches) is essential. In high-performance VLSI circuits a substantial number of interconnections are pipelined (spanning over more than one clock cycle), making the number of needed repeaters too large for manual design. Therefore, an automated tool to insert clocked repeaters, as well as non-clocked repeaters, in the circuit design is necessary to reduce the Register-Transfer-Level (RTL)-to-layout convergence time. This is important as current scaling trends indicate that the number of both clocked and non-clocked repeaters increases exponentially every process generation.
In pipelined interconnects at least two challenges are faced by circuit designers: a) The accurate prediction of the minimum latency that can be achieved between the blocks of a design, given the available routing resources of a semiconductor process, and b) The insertion of buffers and flip-flops in a large number of pipelined nets where interconnect and functional latency constraints are specified at-priori by the circuit designers.